Search found 3 matches

by karthik.venkata2020
Sun Jul 24, 2016 7:13 pm
Forum: Physical Design (PD)
Topic: Why LVT cells are more leaky!
Replies: 1
Views: 12768

Re: Why LVT cells are more leaky!

Because the thickness of gate oxide is less for LVT cells. so gate tunneling current will be more causing more currents to flow through gate.
and also threshold voltage levels of transistor are low. so leakage current will be more and LVT cells are leaky


Best Regards,
G.V.K
by karthik.venkata2020
Mon Feb 22, 2016 3:14 pm
Forum: Physical Design (PD)
Topic: Crosstalk effect & its impact on timing
Replies: 3
Views: 17890

Re: Crosstalk effect & its impact on timing

Hi Vikram, Am adding some points to your question. Shielding: Shielding is a process of Separating Aggressor and Victim Nets with VSS (In general gnd net) net placing in between two crosstalk nets. Thereby we are guarding Victim net with VSS from the High Switching activity of Aggressor Net. There b...
by karthik.venkata2020
Thu Aug 07, 2014 5:35 pm
Forum: Physical Design (PD)
Topic: Differnce clock skew and clock insertion delay?
Replies: 3
Views: 17620

Re: Differnce clock skew and clock insertion delay?

hi all, i am venkata karthik, i want to add some more information to above discussion clock insertion dealy: : The time taken by the clock signal to reach the sink flops from clock source is termed as the clock insertion delay, and the clock insertion delay is depending on two factors they are "...