hi there,
can any one tell me what is the difference between EDT clock and Scan clock. EDT clock is used in EDT compressor logic in TestKompressor ?
Search found 21 matches
- Fri Sep 23, 2016 12:22 am
- Forum: Design For Testing (DFT)
- Topic: EDT Clock vs Scan Clock
- Replies: 0
- Views: 14342
- Wed Aug 24, 2016 6:55 pm
- Forum: Design For Testing (DFT)
- Topic: DFT
- Replies: 0
- Views: 13787
DFT
1. how do we perform parallel simulation and serial simulation in VCS. what is the process and inputs should we take care of ? 2. how do we debug any timing simulation fails at silicon with timing and no timing simulation process ? 3. what is chain pattern test ? 4. even after STA timing closer why ...
- Fri Apr 08, 2016 11:04 pm
- Forum: Design For Testing (DFT)
- Topic: How Sequential Depth helps to Improve Test coverage ?
- Replies: 2
- Views: 15146
Re: How Sequential Depth helps to Improve Test coverage ?
hi renu,
can you please elaborate your answer. and also let me know, this functionality is related to NCP (Named Captured Procedure) cycles ?
can you please elaborate your answer. and also let me know, this functionality is related to NCP (Named Captured Procedure) cycles ?
- Fri Apr 08, 2016 10:56 pm
- Forum: Design For Testing (DFT)
- Topic: What is a lock-up latch & why it used in DFT
- Replies: 4
- Views: 17870
Re: What is a lock-up latch & why it used in DFT
Is lock up latch is same as the synchronizer ? if yes explain how ?
- Mon Feb 22, 2016 7:49 pm
- Forum: Design For Testing (DFT)
- Topic: Test Pattern Simulation
- Replies: 0
- Views: 15056
Test Pattern Simulation
Hello there,
can any one tell me about the mismatches occurred during zero delay simulation after pattern generation in ATPG. As I know there is one mismatch due to pin constraints / cut points. Is there any other mismatch ?
can any one tell me about the mismatches occurred during zero delay simulation after pattern generation in ATPG. As I know there is one mismatch due to pin constraints / cut points. Is there any other mismatch ?
- Mon Feb 22, 2016 7:13 pm
- Forum: Design For Testing (DFT)
- Topic: Pattern Inflation
- Replies: 2
- Views: 12545
Re: Pattern Inflation
hello there, I got my answer the post I have posted about Pattern Inflation. Basically it is one of the drawback of Compression Technique. As we know by doing compression we have the advantages like reduction in TAT and TDV inspite of these advantages there are also some disadvantages of compression...
- Mon Dec 21, 2015 5:35 pm
- Forum: Design For Testing (DFT)
- Topic: Pattern Inflation
- Replies: 2
- Views: 12545
Pattern Inflation
hi guys,
please, can any one tell me about Pattern Inflation? what it is and how it will be used in DFT ?
Thanks in advance !
please, can any one tell me about Pattern Inflation? what it is and how it will be used in DFT ?
Thanks in advance !
- Fri Dec 04, 2015 2:16 pm
- Forum: Design For Testing (DFT)
- Topic: Test procedure file used for EDT and ATPG
- Replies: 2
- Views: 12153
Re: Test procedure file used for EDT and ATPG
Thank you Renu. It is really helpful.
- Thu Nov 26, 2015 5:09 pm
- Forum: Design For Testing (DFT)
- Topic: Test procedure file used for EDT and ATPG
- Replies: 2
- Views: 12153
Test procedure file used for EDT and ATPG
Hi friends.
As we know after scan insertion the tool will generate the TPF (Test Procedure File) to perform 'ATPG. Does it is the same file used for the both ATPG and EDT ? as far as I know there is only one TPF used for ATPG ?
As we know after scan insertion the tool will generate the TPF (Test Procedure File) to perform 'ATPG. Does it is the same file used for the both ATPG and EDT ? as far as I know there is only one TPF used for ATPG ?
- Mon Nov 23, 2015 6:59 pm
- Forum: Design For Testing (DFT)
- Topic: IDDQ Testing Basics
- Replies: 2
- Views: 11591
Re: IDDQ Testing Basics
Hi Renu. I heard that IDDQ testing was used long time ago, but now a days it is avoided due to decrease in the transistor size. And also heard that, it is a special type of testing performed to detect the faults which were not easily detected by the stuck at testing. My question is , the faults whic...