First level,
2 gates. Gate 1 has inputs 0 and A. Gate 2 has inputs B and 1.
Second level
1 gate. Gate 3 has inputs output of gate 1 and output of gate 2.
Note,
In the description of the gates above with boolean function y= A+B' , the first input is A pin and second input is B pin.
Search found 3 matches
- Wed May 28, 2014 11:30 am
- Forum: Digital Design
- Topic: Designing a NAND gate with "my gate"
- Replies: 1
- Views: 9489
- Thu May 01, 2014 11:42 am
- Forum: Physical Design (PD)
- Topic: How does DFT logic affect PD ?
- Replies: 2
- Views: 10740
How does DFT logic affect PD ?
How does mbist logic affect placement ? Will knowing the algorithms used to assign controllers help in floorplan ? How does scan chain affect PD ?
- Thu May 01, 2014 1:18 am
- Forum: IC Fabrication Technology
- Topic: Why silicon is used for the fabrication of IC fabrication.
- Replies: 3
- Views: 31700
Re: Why silicon is used for the fabrication of IC fabricatio
Silicon is less temperature sensitive and freely available.
Initially, Ge was used more than Si as the methods to purify Si weren't developed.
Initially, Ge was used more than Si as the methods to purify Si weren't developed.