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by binod23
Fri Apr 08, 2016 6:57 pm
Forum: Digital Design
Topic: HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
Replies: 0
Views: 6466

HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?

Dear All, I want to record the states of all flipflops in the design as the verilog design is simulated for some fixed number of cycles. I don't have the need to view the waveforms of those signals. I want to use those states for further processing. Please tell how to dump the states of the flipflop...