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I am seeing negative net delay in PT timing report. Is it possible to have negative net delay numbers?

What are the differences between architecture and micro-architecture?

can someone please explain the concept of weak 0 and weak 1?

Why LVT cells have more leakage power?

Can any one please explain in detail, the difference between static & dynamic IR drop?

Technology node is still 45nm. But as Narveer told, this is to get more die per wafer, foundry shrink 45nm geometry to 40nm. So all 45nm GDS are shrunk to 40nm before fabrication.

Thanks Aru ! For detail explantion.

Very informative links. Thanks Aru

Thanks Arun. It helped a lot Can you please reply to my other queries also?

How does lockup latch help with hold violation ?