Search found 22 matches

by RENU
Fri Jul 01, 2016 6:08 pm
Forum: Digital Design
Topic: What is difference between normal PLL and Deskew pll???
Replies: 2
Views: 8860

What is difference between normal PLL and Deskew pll???

What is difference between normal PLL and Deskew pll???
by RENU
Wed Jun 01, 2016 4:10 pm
Forum: Synthesis & Timing
Topic: Different Timing terminologies
Replies: 0
Views: 10260

Different Timing terminologies

Typical Clock Generation Scenario:The oscillator is external to the chip and produces a low frequency (10-50 MHz typical) clock which is used as a reference clock by the on-chip PLL to generate a high-frequency low-jitter clock (200-800 MHz typical). This PLL clock is then fed to a clock divider log...
by RENU
Wed Jun 01, 2016 3:27 pm
Forum: Design For Testing (DFT)
Topic: set input_delay and set output_delay
Replies: 0
Views: 5927

set input_delay and set output_delay

Why we need to set input_delay and set output_delay in our sdc's? How will we decide these numbers at block level and top design level?
by RENU
Mon May 09, 2016 3:15 pm
Forum: Design For Testing (DFT)
Topic: Pattern Inflation
Replies: 2
Views: 3421

Re: Pattern Inflation

Thanks Vikram :) .. your post is really informative.
by RENU
Fri Dec 11, 2015 4:52 pm
Forum: Design For Testing (DFT)
Topic: How Sequential Depth helps to Improve Test coverage ?
Replies: 2
Views: 2376

Re: How Sequential Depth helps to Improve Test coverage ?

Hi Vikram, May be you know as sequential depth is related to capture ( Launc on capture if atspeed), when we want to capture value related to input of non-scannable flop we need extra clock pulse so by increasing seuential depth as 2 you can capture response of that non-scan flop via scanable flop h...
by RENU
Mon Nov 30, 2015 3:10 pm
Forum: Design For Testing (DFT)
Topic: IDDQ Testing Basics
Replies: 2
Views: 1579

Re: IDDQ Testing Basics

Hi Vikram,

You are right IDDQ fault testing is for faults which are not detected by stuckat fault type. It is like top-up patterns. Also, Bridging faults and punch trough faults can be detected by these patterns.So, we use IDDQ patterns for additional fault coverage.

Regards,
Renu
by RENU
Mon Nov 30, 2015 3:03 pm
Forum: Design For Testing (DFT)
Topic: Test procedure file used for EDT and ATPG
Replies: 2
Views: 1915

Re: Test procedure file used for EDT and ATPG

Hi Vikaram, Test Procedure file will be mostly same for EDT(Decompressor-Compression) Insertion and for ATPG (Pattern generation) except for additional EDT constraints. For example : EDT_UPDATE,EDT_CLOCK and other EDT related constraints. Dofile will also have additional constraints with compression...
by RENU
Tue Nov 17, 2015 4:52 pm
Forum: Design For Testing (DFT)
Topic: IDDQ Testing Basics
Replies: 2
Views: 1579

IDDQ Testing Basics

IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By thi...
by RENU
Tue Oct 13, 2015 4:34 pm
Forum: Design For Testing (DFT)
Topic: HOW SCAN WORKS???
Replies: 0
Views: 6927

HOW SCAN WORKS???

how_does_scan_work.pdf
by RENU
Fri Dec 19, 2014 4:49 pm
Forum: Design For Testing (DFT)
Topic: Stitching of positive & negative flops in a scan chain?
Replies: 1
Views: 2453

Stitching of positive & negative flops in a scan chain?

Why we don't stitch positive edge flops then negative edge flops in a scan chain ?