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Please check below post.

viewtopic.php?f=11&t=6

Please check below links:

http://tech.tdzire.com/what-is-minimum- ... bsorption/
http://vlsi.pro/minimum-pulse-width-check/

Correct! Top layer are used for power & ground as they are thicker & hence less resistive. Lower layers are used for signal routing. But there is no hard & fast rule for this.

Standard cells in a library are rectangular with the same height but different widths. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom ...

Verilog interview interview questions with answer.!!!

Hi All, Below links will be helpful for freshers who are preparing for VLSI industry. 1. http://www.exploreroots.com/d0.html 2. http://www.asic.co.in/ 3. http://www.asic-world.com/ 4. http://asic-soc.blogspot.com/ 5. http://chipverification.blogspot.com/ 6. http://only-vlsi.blogspot.com/ 7. http ...

Cache memory is used to store frequently used data/instruction to improve the performance. A processor may have up to 3 level of cache i.e. L1, L2 & L3 cache. Out of these three L1 is fastest & L3 is slowest. The L1 cache typically ranges in size from 8KB to 64KB and uses the high-speed SRAM (static ...

Mahesh, I have documents related to power planning. Please go through them. If still you have any doubt, you can post it here.

You can even make a processor of 10 GHZ or more with today available. Si technology at 45 nm node but why to do so .......???? when it is of no use...... we are shrinking the size not to increase the speed of processor now a days .... it is only for increasing the storage capacity (i.e Memories) for ...