Because of the power consumption and complexity they add to the designs
But there are places where still latch based paths in the designs widely used in the designs ..
Search found 5 matches
- Sun Aug 17, 2014 7:59 pm
- Forum: Frontend Architecture & Verification
- Topic: Why latches are not preferred in synthesized design?
- Replies: 1
- Views: 9924
- Sun Aug 17, 2014 7:54 pm
- Forum: Synthesis & Timing
- Topic: How does lockup latch help with hold violation ?
- Replies: 2
- Views: 10582
- Sun Aug 17, 2014 7:52 pm
- Forum: Synthesis & Timing
- Topic: Reasons for unconstrained endpoints in timing?
- Replies: 1
- Views: 14310
Re: Reasons for unconstrained endpoints in timing?
1) If the endpoint is a sequential cell pin , the clock not reaching the cell
2) if the endpoint is an output port , the missing output delay
2) if the endpoint is an output port , the missing output delay
- Sun Aug 17, 2014 7:47 pm
- Forum: Synthesis & Timing
- Topic: Common path pessimism removal (CPPR)
- Replies: 2
- Views: 12242
Re: Common path pessimism removal (CPPR)
Consider the logic shown in Figure attached where the PVT conditions can vary along the chip. The worst condition for setup check occurs when the launch clock path and the data path have the OCV conditions which result in the largest delays, while the capture clock path has the OCV conditions which ...
- Tue May 13, 2014 6:30 pm
- Forum: Synthesis & Timing
- Topic: why do we need virtual clock
- Replies: 3
- Views: 16135
Re: why do we need virtual clock
There are three advantages of having the virtual clocks 1) Applying the clock latency as explained above 2) In case of the hierarchical designs , if a particular clock does not exist in a block , virtual clock of the same can be used to constrain the I/O ports. 3) It also helps in timing the half cy...