Search found 59 matches

by Narveer
Sat May 10, 2014 6:57 pm
Forum: Physical Design (PD)
Topic: global routing and detail routing
Replies: 1
Views: 1944

Re: global routing and detail routing

The routing problem is typically solved using a two step approach: Global Routing: • Define the routing regions. • Generate a tentative route for each net. • Each net is assigned to a set of routing regions. • Does not specify the actual layout of wires. Detailed Routing: • For each routing region, ...
by Narveer
Sat May 10, 2014 6:54 pm
Forum: Physical Design (PD)
Topic: Possible reasons for routing congestion
Replies: 2
Views: 2448

Re: Possible reasons for routing congestion

Routing congestion can be due to following reasons:
1. High standard cell density in small area.
2. Placement of standard cells near macros.
3. High pin density on one edge of block.
4. Placing macros in the middle of floorplan.
5. High via density due to dense power mash.
by Narveer
Sat May 10, 2014 6:49 pm
Forum: Physical Design (PD)
Topic: low power design techniques in vlsi
Replies: 1
Views: 2345

Re: low power design techniques in vlsi

Below are various low power techniques. Design Level: Multi VT, clock gating, power gating, multi VDD and Dynamic Voltage and Frequency Scaling (DVFS). Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET. Search in google to know details of each technique. http://vlsi-soc.blogsp...
by Narveer
Wed May 07, 2014 5:38 pm
Forum: Physical Design (PD)
Topic: steps involved in designing an optimal pad ring
Replies: 1
Views: 2178

Re: steps involved in designing an optimal pad ring

Steps involved in designing an optimal padring: 1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less. 2. Ensure that the Padring full-fills the ESD requirement, Identify the power-domains,split the do...
by Narveer
Tue May 06, 2014 10:48 pm
Forum: Physical Design (PD)
Topic: VLSI Physical design basics
Replies: 2
Views: 2265

Re: VLSI Physical design basics

Thanks sandeep for sharing this. "Gate to GDS Place & Route Methodology" by Lee Eng Han is very good book on physical design. Unfortunately only first chapter is available.
by Narveer
Mon May 05, 2014 4:21 pm
Forum: Physical Design (PD)
Topic: floorplanning: spacing between two macros/memories
Replies: 2
Views: 10755

Re: floorplanning: spacing between two macros/memories

The formula to calculate spacing between two macro is (width+spacing x number of pins /vertical routing layers) + spacing . It is better adding an additional spacing because you can avoid violation with the side of macros. Tips for macro Placement /Floorplanning : 1. Place macros around chip periphe...
by Narveer
Sun May 04, 2014 8:39 pm
Forum: Device Physics
Topic: Why MOSFET is more popular than BJT?
Replies: 1
Views: 1859

Re: Why MOSFET is more popular than BJT?

Compared to the bipolar junction transistor (BJT), MOS transistor have below advantages : 1. MOS transistor occupies a relatively smaller silicon area compared to BJT. More number of transistors can fitted in a given area. 2. MOS transistor involves fewer fabrication step (less number of masks). so ...
by Narveer
Fri May 02, 2014 8:24 pm
Forum: Physical Design (PD)
Topic: How does DFT logic affect PD ?
Replies: 2
Views: 2296

Re: How does DFT logic affect PD ?

MBIST (Memory built-in self-test) logic is inserted to test the memories. It contains MBIST processor & wrapper around the memories. MBIST processor controls the wrapper & generates various control signals during the memory testing. A single block may have multiple processors depending on the number...