Search found 25 matches
- Mon Apr 14, 2014 10:02 pm
- Forum: Design For Testing (DFT)
- Topic: What is a lock-up latch & why it used in DFT
- Replies: 4
- Views: 14707
What is a lock-up latch & why it used in DFT
What is a lock-up latch? Why it is used in DFT? What are its implication on timing?
- Sun Apr 13, 2014 11:37 pm
- Forum: Frontend Architecture & Verification
- Topic: Asynchronous vs synchronous reset
- Replies: 1
- Views: 8695
Asynchronous vs synchronous reset
What is the difference between asynchronous and synchronous reset? Explain the advantages and disadvantages of both?
- Sun Apr 13, 2014 11:35 pm
- Forum: Digital Design
- Topic: NAND vs NOR gate
- Replies: 0
- Views: 7236
NAND vs NOR gate
Which gate is normally preferred while implementing circuits using CMOS logic NAND or NOR? Why?
- Sun Apr 13, 2014 11:33 pm
- Forum: Digital Design
- Topic: Race around condition vs metastability
- Replies: 0
- Views: 7979
Race around condition vs metastability
What is the difference between race around condition and metastability state of a flip-flop?
- Sun Apr 13, 2014 1:43 pm
- Forum: Physical Design (PD)
- Topic: Crosstalk effect & its impact on timing
- Replies: 3
- Views: 18230
Crosstalk effect & its impact on timing
What is crosstalk? What is the effect of crosstalk on timing? How to minimize crosstalk?