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Hi,

suppose we have a FF1 which is scannable with scan clock and its output is connected to FF2 which is non scannable. I mean FF1 is connected with scan clock and FF2 is connected with normal clock. If we increase sequential depth , then how it will increase or effect test coverage ?

Hi folks, we know to maintain the signal pulse width constant by inserting repeater or buffers , with out degradation in it from source to destination in clock path or in data path. How can we know the specific no of repeaters to be inserted in the clock path or data path ? Is there any equation to ...

Hi,

how the sequential depth and abort limit in DFT effect the test coverage ? What exactly happen if these are changed while testing the design ?

Thank you. It's very useful info.

Can you please explain what is shielding and up sizing / down sizing techniques ?

Hello, Can any one tell me about the different metal layers used in the chip layout. I know that the metal layers are used for routing.But I have a confusion, all the core cells are placed on core area while metal layers are used for routing. Is it true , core area is used only for placement of cell...

Thank you. Its helpful to me.

Hi , Actually we can have three combinations: 1) All positive 2) All negative 3) Negative followed by positive but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not p...

Hi Gayatri, As we know in DFT , scan cells are connected together to form a scan chain. These scan chains forms scan groups. In DFT with this inserted scan chains the netlist is moved to further process in PD. In PD depending up on the placement and timing the order of the scan cells will be changed...

Hi there,

As we all know that the height of the standard cells in .lib file is same for all the cells. Can anyone tell me the exact reason and the importance / benefits of having same height ??