Hi,
suppose we have a FF1 which is scannable with scan clock and its output is connected to FF2 which is non scannable. I mean FF1 is connected with scan clock and FF2 is connected with normal clock. If we increase sequential depth , then how it will increase or effect test coverage ?
Search found 21 matches
- Tue Nov 17, 2015 10:03 pm
- Forum: Design For Testing (DFT)
- Topic: How Sequential Depth helps to Improve Test coverage ?
- Replies: 2
- Views: 12994
- Tue Apr 14, 2015 7:16 pm
- Forum: Physical Design (PD)
- Topic: Insertion of Repeaters / Buffers in the clock path
- Replies: 1
- Views: 8936
Insertion of Repeaters / Buffers in the clock path
Hi folks, we know to maintain the signal pulse width constant by inserting repeater or buffers , with out degradation in it from source to destination in clock path or in data path. How can we know the specific no of repeaters to be inserted in the clock path or data path ? Is there any equation to ...
- Sat Apr 11, 2015 9:27 pm
- Forum: Design For Testing (DFT)
- Topic: Effect of Sequential depth and Abort limit on Test Coverge
- Replies: 1
- Views: 9681
Effect of Sequential depth and Abort limit on Test Coverge
Hi,
how the sequential depth and abort limit in DFT effect the test coverage ? What exactly happen if these are changed while testing the design ?
how the sequential depth and abort limit in DFT effect the test coverage ? What exactly happen if these are changed while testing the design ?
- Wed Apr 08, 2015 12:37 pm
- Forum: Physical Design (PD)
- Topic: floorplanning: spacing between two macros/memories
- Replies: 2
- Views: 22502
Re: floorplanning: spacing between two macros/memories
Thank you. It's very useful info.
- Wed Apr 08, 2015 12:29 pm
- Forum: Physical Design (PD)
- Topic: Crosstalk effect & its impact on timing
- Replies: 3
- Views: 19254
Re: Crosstalk effect & its impact on timing
Can you please explain what is shielding and up sizing / down sizing techniques ?
- Tue Apr 07, 2015 5:33 pm
- Forum: Physical Design (PD)
- Topic: Metal Layers in the chip
- Replies: 3
- Views: 20717
Metal Layers in the chip
Hello, Can any one tell me about the different metal layers used in the chip layout. I know that the metal layers are used for routing.But I have a confusion, all the core cells are placed on core area while metal layers are used for routing. Is it true , core area is used only for placement of cell...
- Tue Apr 07, 2015 5:24 pm
- Forum: Physical Design (PD)
- Topic: Height of standard cells
- Replies: 2
- Views: 8780
Re: Height of standard cells
Thank you. Its helpful to me.
- Mon Apr 06, 2015 10:12 pm
- Forum: Design For Testing (DFT)
- Topic: Stitching of positive & negative flops in a scan chain?
- Replies: 1
- Views: 10115
Re: Stitching of positive & negative flops in a scan chain?
Hi , Actually we can have three combinations: 1) All positive 2) All negative 3) Negative followed by positive but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not p...
- Mon Apr 06, 2015 9:58 pm
- Forum: Physical Design (PD)
- Topic: How does DFT logic affect PD ?
- Replies: 2
- Views: 8902
Re: How does DFT logic affect PD ?
Hi Gayatri, As we know in DFT , scan cells are connected together to form a scan chain. These scan chains forms scan groups. In DFT with this inserted scan chains the netlist is moved to further process in PD. In PD depending up on the placement and timing the order of the scan cells will be changed...
- Mon Apr 06, 2015 9:43 pm
- Forum: Physical Design (PD)
- Topic: Height of standard cells
- Replies: 2
- Views: 8780
Height of standard cells
Hi there,
As we all know that the height of the standard cells in .lib file is same for all the cells. Can anyone tell me the exact reason and the importance / benefits of having same height ??
As we all know that the height of the standard cells in .lib file is same for all the cells. Can anyone tell me the exact reason and the importance / benefits of having same height ??