Search found 59 matches

by Narveer
Thu Apr 10, 2014 10:50 am
Forum: IC Fabrication Technology
Topic: What are differences between Si(111), Si(110) and Si(100) ?
Replies: 1
Views: 4358

Re: What are differences between Si(111), Si(110) and Si(100

In Anisotropic Etching we say that etch rate in one orientation say (100) is higher than etch rate in another orientation say (111) i.e. we get less etching in (111) plane and more etching in (100) plane and we are able to form V -shape etched surface in Silicon wafers. It means both (100) plane and...
by Narveer
Thu Apr 10, 2014 7:33 am
Forum: Interview Material
Topic: VLSI Design Interview Questions!
Replies: 1
Views: 2896

VLSI Design Interview Questions!

I have attached a document related to VLSI design interview questions. I contains a lot of questions that are commonly asked in written tests and interviews. The question are of good quality and covering important concepts of VLSI design. Hope this will help members in preparing for interviews. If y...
by Narveer
Wed Apr 09, 2014 9:17 pm
Forum: Useful Links
Topic: National Programme on Technology Enhanced Learning (NPTEL)
Replies: 0
Views: 1419

National Programme on Technology Enhanced Learning (NPTEL)

The National Programme on Technology Enhanced Learning (NPTEL) is a Government of India sponsored collaborative educational programme. By developing curriculum-based video and web courses the programme aims to enhance the quality of engineering education in India. It is being jointly carried out by ...
by Narveer
Wed Apr 09, 2014 5:29 pm
Forum: Device Physics
Topic: Why PMOS always have bigger size than NMOS?
Replies: 2
Views: 4308

Re: Why PMOS always have bigger size than NMOS?

NMOS has electrons as majority charge carriers and PMOS has hole as majority charge carriers. Electrons has mobility ~2.7 times higher the holes. The main reason behind making PMOS larger is that rise time and fall time of gate should be equal and for this the resistance of the NMOS and PMOS should ...
by Narveer
Wed Apr 09, 2014 4:12 pm
Forum: Synthesis & Timing
Topic: What is a false path and what is multi-cycle path?
Replies: 1
Views: 1762

Re: What is a false path and what is multi-cycle path?

False path is that timing path for which STA tool is instructed to ignore its timing requirements (setup, hold). Typically false paths are present in the design because of the following reasons. 1) The path is functionally never exercised. 2) There are some unused ports of a reused IP which form th...
by Narveer
Wed Apr 09, 2014 3:57 pm
Forum: Device Physics
Topic: PMOS as pullup & NMOS as pull down. why?
Replies: 1
Views: 2090

Re: PMOS as pullup & NMOS as pull down. why?

NMOS can pull-down output to 0V but it can pull-up maximum to VDD-Vtn. So it is bad-1 and good-0. PMOS can pull-up output to VDD but it can pull-down to Vtp. So it is bad-0 but good-1 where Vtn,Vtp are threshold voltage for NMOS and PMOS respectively. Also check below link. http://www.evlsi.com/view...
by Narveer
Wed Apr 09, 2014 3:51 pm
Forum: Device Physics
Topic: What will happen if we swap the transistors of an inverter?
Replies: 2
Views: 3193

Re: What will happen if we swap the transistors of an invert

If we swap the transistors of an inverter that means NMOS will acts as pull-up transistor and PMOS acts as pull-down. So 1. when input is HIGH then PMOS is in cut-off region and NMOS pull-up output to HIGH state. But output voltage will Vtn( i.e threshold voltage for NMOS) less than VDD. NMOS is BAD...
by Narveer
Wed Apr 09, 2014 10:27 am
Forum: Synthesis & Timing
Topic: Understanding basic of STA (Static Timing Analysis)
Replies: 0
Views: 1724

Understanding basic of STA (Static Timing Analysis)

I have attached a good document for understanding basic of STA.