eVLSI.com - VLSI Design Forum

Digital Design
All queries related to number system, flip-flops, logic designs and CMOS based digital circuits.

Physical Design (PD)
All question related to floorplanning, power planning, placement, clock tree synthesis (CTS), routing, DRC cleaning, LVS, power, IR drop, Electromigration (EM), ESD, package.

Synthesis & Timing
Synthesis, timing closure, fixing setup & hold, constraints related questions can be asked here.

Design For Testing (DFT)
SCAN, Boundary SCAN, MBIST, ATPG, JTAG, ATE, DFT simulations.

Frontend Architecture & Verification
Post questions related to VHDL, Verilog, System Verilog, Architecture & Verification in this section.

Analog and Mixed Signal (AMS) Design
Analog and Mixed Signal (AMS) Design.

Embedded Systems
Post related to Microprocessor, Microcontroller & real time system.

Interview Material
Post documents related to VLSI Design Interview Questions, Physical Design Interview Questions here.

Job info
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