Physical Design (PD)

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Metal Layers in the chip

Last post by nithin « Fri Aug 24, 2018 12:05 pm
Replies: 3
by vikramrajput » Tue Apr 07, 2015 5:33 pm

3 Replies

4322 Views

Last post by nithin
Fri Aug 24, 2018 12:05 pm
Understanding ICV Back End Of Line Runsets for Dummy Metal Fill

Last post by pruthwish « Sun Mar 26, 2017 8:50 pm

by pruthwish » Sun Mar 26, 2017 8:50 pm

0 Replies

1838 Views

Last post by pruthwish
Sun Mar 26, 2017 8:50 pm
Why LVT cells are more leaky!

Last post by karthik.venkata2020 « Sun Jul 24, 2016 7:13 pm
Replies: 1
by Amit » Tue Jan 06, 2015 3:43 pm

1 Replies

5989 Views

Last post by karthik.venkata2020
Sun Jul 24, 2016 7:13 pm
what is the difference between endcap and filler?

Last post by Venkateshgubbi « Fri May 13, 2016 11:02 pm
Replies: 1
by nsuresh60 » Thu Dec 31, 2015 12:26 pm

1 Replies

4378 Views

Last post by Venkateshgubbi
Fri May 13, 2016 11:02 pm
Crosstalk effect & its impact on timing

Last post by karthik.venkata2020 « Mon Feb 22, 2016 3:14 pm
Replies: 3
by Vijay » Sun Apr 13, 2014 1:43 pm

3 Replies

7331 Views

Last post by karthik.venkata2020
Mon Feb 22, 2016 3:14 pm
Possible reasons for routing congestion

Last post by nsuresh60 « Thu Dec 31, 2015 12:49 pm
Replies: 2
by Vijay » Sat May 10, 2014 2:33 pm

2 Replies

2478 Views

Last post by nsuresh60
Thu Dec 31, 2015 12:49 pm
9 track and 12 track in standard cells

Last post by tejaNSRP « Mon Nov 30, 2015 2:59 pm
Replies: 2
by Vijay » Tue Apr 15, 2014 11:59 am

2 Replies

6195 Views

Last post by tejaNSRP
Mon Nov 30, 2015 2:59 pm
CTS Algorithm Skew values

Last post by sebinkurianp « Mon May 18, 2015 11:31 am

by sebinkurianp » Mon May 18, 2015 11:31 am

0 Replies

7363 Views

Last post by sebinkurianp
Mon May 18, 2015 11:31 am
Insertion of Repeaters / Buffers in the clock path

Last post by Narveer « Wed Apr 15, 2015 9:57 am
Replies: 1
by vikramrajput » Tue Apr 14, 2015 7:16 pm

1 Replies

2320 Views

Last post by Narveer
Wed Apr 15, 2015 9:57 am
floorplanning: spacing between two macros/memories

Last post by vikramrajput « Wed Apr 08, 2015 12:37 pm
Replies: 2
by Vijay » Mon May 05, 2014 3:55 pm

2 Replies

10961 Views

Last post by vikramrajput
Wed Apr 08, 2015 12:37 pm
Height of standard cells

Last post by vikramrajput « Tue Apr 07, 2015 5:24 pm
Replies: 2
by vikramrajput » Mon Apr 06, 2015 9:43 pm

2 Replies

2080 Views

Last post by vikramrajput
Tue Apr 07, 2015 5:24 pm
How does DFT logic affect PD ?

Last post by vikramrajput « Mon Apr 06, 2015 9:58 pm
Replies: 2
by GayathriJeyaram » Thu May 01, 2014 11:42 am

2 Replies

2315 Views

Last post by vikramrajput
Mon Apr 06, 2015 9:58 pm
VLSI Physical design basics

Last post by vikramrajput « Mon Apr 06, 2015 9:38 pm
Replies: 2
by sandeep » Tue May 06, 2014 9:15 pm

2 Replies

2282 Views

Last post by vikramrajput
Mon Apr 06, 2015 9:38 pm
clock tree synthesis using clock inverters only

Last post by Netrapal « Wed Mar 18, 2015 11:40 am

by Netrapal » Wed Mar 18, 2015 11:40 am

0 Replies

4359 Views

Last post by Netrapal
Wed Mar 18, 2015 11:40 am
Static vs Dynamic IR Drop

Last post by Amit « Tue Jan 06, 2015 3:34 pm

by Amit » Tue Jan 06, 2015 3:34 pm

0 Replies

1927 Views

Last post by Amit
Tue Jan 06, 2015 3:34 pm
Cheers for VLSI

Last post by sandeep « Wed Sep 03, 2014 10:12 am

by sandeep » Wed Sep 03, 2014 10:12 am

0 Replies

1737 Views

Last post by sandeep
Wed Sep 03, 2014 10:12 am
power planing

Last post by Narveer « Wed Aug 27, 2014 2:21 pm
Replies: 1
by mahesht » Tue Aug 26, 2014 12:01 pm

1 Replies

1859 Views

Last post by Narveer
Wed Aug 27, 2014 2:21 pm
Differnce clock skew and clock insertion delay?

Last post by Arvind « Fri Aug 08, 2014 11:07 am
Replies: 3
by Arvind » Wed Apr 09, 2014 3:53 pm

3 Replies

9535 Views

Last post by Arvind
Fri Aug 08, 2014 11:07 am
What is IR Drop Analysis? How it effects the timing?

Last post by rajeshs « Fri Jun 27, 2014 2:15 pm
Replies: 1
by Netrapal » Sun Jun 22, 2014 5:01 pm

1 Replies

1928 Views

Last post by rajeshs
Fri Jun 27, 2014 2:15 pm
tools used for IR analysis

Last post by rajeshs « Fri Jun 27, 2014 12:51 pm
Replies: 1
by Netrapal » Sun Jun 22, 2014 5:02 pm

1 Replies

1793 Views

Last post by rajeshs
Fri Jun 27, 2014 12:51 pm
local skew, global skew & useful skew

Last post by Narveer « Sun May 11, 2014 11:41 am
Replies: 1
by Netrapal » Sat May 10, 2014 10:42 pm

1 Replies

6954 Views

Last post by Narveer
Sun May 11, 2014 11:41 am
global routing and detail routing

Last post by Narveer « Sat May 10, 2014 6:57 pm
Replies: 1
by Vijay » Sat May 10, 2014 1:31 pm

1 Replies

1977 Views

Last post by Narveer
Sat May 10, 2014 6:57 pm
low power design techniques in vlsi

Last post by Narveer « Sat May 10, 2014 6:49 pm
Replies: 1
by Arvind » Sat May 10, 2014 2:22 pm

1 Replies

2365 Views

Last post by Narveer
Sat May 10, 2014 6:49 pm
why macros design don't use all the available metal layers

Last post by gangadharn « Thu May 08, 2014 5:03 pm
Replies: 1
by Vijay » Wed May 07, 2014 3:08 pm

1 Replies

1958 Views

Last post by gangadharn
Thu May 08, 2014 5:03 pm
steps involved in designing an optimal pad ring

Last post by Narveer « Wed May 07, 2014 5:38 pm
Replies: 1
by Vijay » Wed May 07, 2014 3:03 pm

1 Replies

2209 Views

Last post by Narveer
Wed May 07, 2014 5:38 pm

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