Tem effect on mobility

Device Physics doubts related to diode, transistor, BJT, MOSFET, JFET.
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Joined: Mon Sep 22, 2014 9:09 pm

Tem effect on mobility

Post by prasanna1605 » Sun Sep 28, 2014 2:15 pm

Hi all,

I am new to this forum but felt it will be useful .

I have three ques please help me in them.

1.What is the effect of temperature on threshold voltage and mobility?
2.What is the effect of gate voltage on mobility?
3.Avg and dynamic power of cmos ?

Pardeep Kumar
Posts: 40
Joined: Tue Apr 08, 2014 3:21 pm

Re: Tem effect on mobility

Post by Pardeep Kumar » Tue Sep 30, 2014 2:37 pm

Threshold voltage decreases linearly with increase in temperature. At higher temperature contribution in the formation of channel carriers from thermal effect will be more and lesser gate voltage will be required to form the channel.

The mobility of the carriers has a nonlinear dependence on temperature. The mobility is influenced by two phenomena:
1. Phonon scattering, due to random thermal vibrations of the semiconductor atom, which increases with the temperature.
2. Coulomb scattering, due to the doping atoms repelling (attracting) electrons (holes) that appear in their vicinity.
When the doping concentration is very high, Coulomb scattering dominates and mobility increases with temperature. However, at lower doping concentrations phonon scattering dominates; thus, mobility decreases with temperature.

At low-fields and bulk samples carriers are almost in equilibrium with the lattice vibrations and the low-field mobility is mainly affected by phonon and Coulomb scattering. At higher electric fields mobility becomes field-dependent parameter and it decreases with increasing electric field due to increased lattice scattering at higher carrier energies.

Power dissipation in CMOS circuits comes from two components
Static dissipation due to
(a) subthreshold conduction through OFF transistors
(b) tunneling current through gate oxide
(c) leakage through reverse-biased diodes

and Dynamic dissipation due to
(a) charging and discharging of load capacitances
(b) short circuit current while both PMOS and NMOS networks are partially ON

Total Power Dissipation = Static Power Dissipation + Dynamic Power Dissipation

The average power dissipation will be the total power dissipation divided by the total time into consideration.
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