What is latchup? Explain the method to prevent it?

Device Physics doubts related to diode, transistor, BJT, MOSFET, JFET.
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Arvind
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Joined: Wed Apr 09, 2014 3:11 pm
Location: Noida, India

What is latchup? Explain the method to prevent it?

Post by Arvind » Thu Apr 10, 2014 2:55 pm

What is latchup? Explain the method to prevent it?

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Narveer
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Location: Bangalore, INDIA

Re: What is latchup? Explain the method to prevent it?

Post by Narveer » Thu Apr 10, 2014 3:03 pm

Latch-Up is a condition in which the parasitic components give rise to the establishment of low-resistance conducting path between Vdd and Vss with disastrous result. The parasitic NPN and PNP transistors make a SCR structure and if their dc current gain product is greater than 1, then a self-sustained structure will provide a path to ground.

To prevent this, increase the doping of both Well and Bulk.

But it will change the other parameters also e.g. threshold voltage etc. And, as a designer we can not decide the doping levels. Then, we have to play only with layout structure.

So, Latch-Up can be prevented by following methods:

1.) Including as many substrate/well contacts as possible to capture
more and more carriers.
2.) Make substrate contact close to source.
3.) Use Guard Rings (Important for I/O section, because they are most
sensitive to Latch-up as they interact with external world)
4.) Limiting the Supply current on the chip

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