Why is number of inputs of a CMOS gate are limited to four

Device Physics doubts related to diode, transistor, BJT, MOSFET, JFET.
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Arvind
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Joined: Wed Apr 09, 2014 3:11 pm
Location: Noida, India

Why is number of inputs of a CMOS gate are limited to four

Post by Arvind » Fri Apr 11, 2014 5:28 pm

Why is the number of inputs of a CMOS gate (e.g. NAND or NOR gates) are usually limited to four?

nikhilp
Posts: 3
Joined: Tue Apr 15, 2014 10:52 am

Re: Why is number of inputs of a CMOS gate are limited to fo

Post by nikhilp » Tue Apr 15, 2014 12:30 pm

I guess this is to limit the stack. NMOS stack for NAND and PMOS stack for NOR. Longer the stack, more will be

1. delay
2. higher input cap for int input signals.

Also, I am not sure but i read it somewhere that increasing the stack also increases the varibility a lot and anylysis like monte carlo take a lot of time.

RAMKESH SHARMA
Posts: 2
Joined: Tue Apr 15, 2014 11:50 am

Re: Why is number of inputs of a CMOS gate are limited to fo

Post by RAMKESH SHARMA » Tue Apr 15, 2014 12:35 pm

Let's understand it with the help of an Example::--- Let's take CMOS NAND Gate: if no. of inputs are 8, It means 8 NMOS's are in Series and we know , In Series Resistance will be added.So after addition Series Resistance will be high , Consequently Delay of the Gate will be High and we can Say , Unacceptable for Our Design. Generally we use 3 or 4 inputs Gates in Our Design because we know that if we use more than 4 inputs , Delay will Drastically increase and Impact the Design Performance. But One thing I would say that It is not Hard and Fast Rule that no. of inputs are limited to Four. We can use less or more no. of input Gates but it depends upon our Delay Requirements. As we always want Faster Design so generally this no. should be less.

P.S. If you have any Confusion, Feel free to Ask. Any comment , Most Welcome!!! ThanX...

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