In an interview I was asked the question:
What is the maximum access bandwidth of 64bit, 100MHz, DDR SDRAM with latencies as 3-2-2.5-0.5. Also, calculate the bandwidth when a new random address is applied after 4 words read.
Any idea, how to solve this. I can calculate the best case bandwith, but don't know how to calculate with latencies.
Thanks in advance
All queries related to number system, flip-flops, logic designs and CMOS based digital circuits.
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