how to prevent metastability

All queries related to number system, flip-flops, logic designs and CMOS based digital circuits.
Post Reply
Netrapal
Posts: 19
Joined: Sat May 10, 2014 10:26 pm
Location: Gurgaon, India

how to prevent metastability

Post by Netrapal »

What is metastability? What are the various ways to prevent it?
Dhivakar
Posts: 1
Joined: Tue Jul 28, 2015 11:33 pm

Re: how to prevent metastability

Post by Dhivakar »

In reality one cannot avoid metastability...but we can tolerate it by the following ways ......

1)by making sure the clock period is long enough to allow for the resolution of metastable states(quasi-stable) and
for the delay of whatever logic may be in the path to the next flip-flop. This approach, while simple, is rarely
practical given the performance requirements of most modern designs.


2)The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. This does, however, increase the latency in the synchronous logic's observation of input changes.
Post Reply