HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?

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binod23
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Joined: Fri Apr 08, 2016 6:55 pm

HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?

Post by binod23 » Fri Apr 08, 2016 6:57 pm

Dear All,


I want to record the states of all flipflops in the design as the verilog design is simulated for some fixed number of cycles. I don't have the need to view the waveforms of those signals. I want to use those states for further processing. Please tell how to dump the states of the flipflops corresponding to each simulation cycle ? I am ready to use any simulator --vcs/ncsim/modelsim/icarus verilog.

I doubt if the vcd file which is generated would serve my purpose as I don't know any method to open vcd files except gtkwave that I don't want (as waveforms are not needed).

Please help. It is urgent.

Thanks In Advance

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