Antenna effect in CMOS layout

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Antenna effect in CMOS layout

Post by Arvind » Thu Apr 10, 2014 2:35 pm

What is the antenna effect in cmos layout? What are the design solutions to reduce antenna effect?

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Re: Antenna effect in CMOS layout

Post by Narveer » Thu Apr 10, 2014 2:45 pm

During the Fabrication Process the large amount of charge is induced in plasma etching, ion implantation and in other processes. If a large interconnect (Poly or other Conducting material) is connected to the Gate of a MOSFET, then this larger conducting material will act as Antenna and will receive the induced charge of the Fabrication Process.

The charge due to these extra carriers might be too much for the thin gate to handle it, and it may also damage the thin oxide layer. So, Antenna effect may result in breakdown of Gate Oxide or degrade the I-V Characteristics.

To avoid the antenna effect we need to avoid large Interconnect Area to Gate of a MOSFET or we can also use the diode placed near the MOSFET, so that the diode will provide a conductive path to substrate, if the induced charge is above a limit.

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