How does DFT logic affect PD ?

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How does DFT logic affect PD ?

Post by GayathriJeyaram » Thu May 01, 2014 11:42 am

How does mbist logic affect placement ? Will knowing the algorithms used to assign controllers help in floorplan ? How does scan chain affect PD ?

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Re: How does DFT logic affect PD ?

Post by Narveer » Fri May 02, 2014 8:24 pm

MBIST (Memory built-in self-test) logic is inserted to test the memories. It contains MBIST processor & wrapper around the memories. MBIST processor controls the wrapper & generates various control signals during the memory testing. A single block may have multiple processors depending on the number of memories, memory size, power and memory placement. Memory placed nearby are grouped together & controlled by a single processor. Memory placement information needs to be given to the DFT team in form of DEF & floorplan snapshot (optional). If memories are not grouped properly according to their physical location i.e memories under same processors are sitting far apart. This will lead to MBIST logic spreading. This may have impact on MBIST timing due to long paths or increase in congestion due to lots of criss-cross.

Knowledge of MBIST algorithms is not required for floorplanning. ... ering.html

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Re: How does DFT logic affect PD ?

Post by vikramrajput » Mon Apr 06, 2015 9:58 pm

Hi Gayatri,

As we know in DFT , scan cells are connected together to form a scan chain. These scan chains forms scan groups. In DFT with this inserted scan chains the netlist is moved to further process in PD. In PD depending up on the placement and timing the order of the scan cells will be changed i,e the modules in the netlist are moved around to meet timing in the design. This process is known as "Scan chain reordering". This modified netlist is given back to the DFT to perfom test. And this iterative process continues till they satisfied. So ,the order of the scan chains will effect the DFT , if there has beeb any modification in PD. And also it will effect PD , as it has been modified by DFT.

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