steps involved in designing an optimal pad ring

All question related to floorplanning, power planning, placement, clock tree synthesis (CTS), routing, DRC cleaning, LVS, power, IR drop, Electromigration (EM), ESD, package.
Post Reply
Vijay
Posts: 25
Joined: Sun Apr 13, 2014 1:39 pm
Location: Bangalore, India

steps involved in designing an optimal pad ring

Post by Vijay »

What are the steps involved in designing an optimal pad ring?
User avatar
Narveer
Posts: 59
Joined: Tue Apr 08, 2014 11:29 am
Location: Bangalore, INDIA

Re: steps involved in designing an optimal pad ring

Post by Narveer »

Steps involved in designing an optimal padring:
1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less.
2. Ensure that the Padring full-fills the ESD requirement, Identify the power-domains,split the domains, Ensure common ground across all the domains.
3. Ensure the padring has full-filled the SSN(Simultaneous Switching Noise) requirement.
4. Placing Transfer-cell Pads in the cross power-domains, for different height pads, tohave rail connectivity.
5. Ensure that the design has sufficient core power-pads.
6. Choose the Drive-strenght of the pads based on the current requirements,timing.
7. Ensure that there is separate analog ground and power pads.
8. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O's.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs float.
9. Ensure that oscillator-pads are used for clock inputs.
10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength.
11. Breaker-pads are used to break the power-ring, and to isolate the power-structure across the pads.
12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin.
13. In case if required , place pads with capacitance.related information.
Post Reply