why macros design don't use all the available metal layers

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Vijay
Posts: 25
Joined: Sun Apr 13, 2014 1:39 pm
Location: Bangalore, India

why macros design don't use all the available metal layers

Post by Vijay » Wed May 07, 2014 3:08 pm

If the full chip design is routed by 7 layer metal, why macros are designed using 4LM instead of using 7LM?

gangadharn
Posts: 1
Joined: Wed May 07, 2014 2:41 pm

Re: why macros design don't use all the available metal laye

Post by gangadharn » Thu May 08, 2014 5:03 pm

Hi Vijay,

If you treat macro's similar standard cells can have answer to your question.

Well here is my understanding :
1) Any cells (Macro and Standard) used in PD, has guidance to use as min as metal layer. So that remaining layer can be used by full chip for clock and signal routing.
2) Let assume a block has 10 stack of macro as one side of floor plan (Because design requirement). Now to access the bottom macro from core logic you need route metal. If macro would had used all metal inside, then there is no no metal to access bottom macros.

I hope above to point help you for your question.

Regards,
Gangadhar Naik

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