low power design techniques in vlsi

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Arvind
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Joined: Wed Apr 09, 2014 3:11 pm
Location: Noida, India

low power design techniques in vlsi

Post by Arvind » Sat May 10, 2014 2:22 pm

What are various low power design techniques used in vlsi design?

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Narveer
Posts: 59
Joined: Tue Apr 08, 2014 11:29 am
Location: Bangalore, INDIA

Re: low power design techniques in vlsi

Post by Narveer » Sat May 10, 2014 6:49 pm

Below are various low power techniques.
Design Level: Multi VT, clock gating, power gating, multi VDD and Dynamic Voltage and Frequency Scaling (DVFS).
Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET.

Search in google to know details of each technique.

http://vlsi-soc.blogspot.in/2012/08/clo ... -cell.html
http://vlsi-soc.blogspot.in/2012/07/clock-gating.html
http://vlsi-soc.blogspot.in/2012/08/power-gating.html
http://vlsi-soc.blogspot.in/2013/03/sta ... ating.html

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