Metal Layers in the chip

All question related to floorplanning, power planning, placement, clock tree synthesis (CTS), routing, DRC cleaning, LVS, power, IR drop, Electromigration (EM), ESD, package.
Post Reply
Posts: 21
Joined: Mon Apr 06, 2015 9:30 pm

Metal Layers in the chip

Post by vikramrajput » Tue Apr 07, 2015 5:33 pm


Can any one tell me about the different metal layers used in the chip layout. I know that the metal layers are used for routing.But I have a confusion, all the core cells are placed on core area while metal layers are used for routing. Is it true , core area is used only for placement of cells and macros while metal layers are used only for routing ?? And there are some metal layers which are used only for some specific purpose like power and ground routing .And other layers are used for some other purpose ?
Please help me out in this.

User avatar
Posts: 59
Joined: Tue Apr 08, 2014 11:29 am
Location: Bangalore, INDIA

Re: Metal Layers in the chip

Post by Narveer » Sat Apr 11, 2015 10:30 am

Correct! Top layer are used for power & ground as they are thicker & hence less resistive. Lower layers are used for signal routing. But there is no hard & fast rule for this.

Posts: 3
Joined: Thu Dec 31, 2015 12:13 pm
Location: bengaluru

Re: Metal Layers in the chip

Post by nsuresh60 » Thu Dec 31, 2015 2:14 pm

How to decide a chip will require certain number of metal layers? how to decide it? what are the considerations?

Posts: 1
Joined: Fri Jul 20, 2018 7:28 pm

Re: Metal Layers in the chip

Post by nithin » Fri Aug 24, 2018 12:05 pm

but while manufacturing is it lower metal layers will get manufacture first?

Post Reply