Differnce clock skew and clock insertion delay?

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Arvind
Posts: 45
Joined: Wed Apr 09, 2014 3:11 pm
Location: Noida, India

Differnce clock skew and clock insertion delay?

Post by Arvind » Wed Apr 09, 2014 3:53 pm

What is the difference between clock skew and clock insertion delay?

vimalraj
Posts: 1
Joined: Thu Apr 10, 2014 9:02 am

Re: Differnce clock skew and clock insertion delay?

Post by vimalraj » Thu Apr 10, 2014 9:07 am

Hai

Clock Insertion Delay : this is the time taken by the clock signal to reach the register from its source point.

Clock Skew : this is the difference between the insertion delay of two registers.


correct me if i am wrong.

thank you

karthik.venkata2020
Posts: 3
Joined: Sun Apr 20, 2014 11:06 am

Re: Differnce clock skew and clock insertion delay?

Post by karthik.venkata2020 » Thu Aug 07, 2014 5:35 pm

hi all,
i am venkata karthik,

i want to add some more information to above discussion

clock insertion dealy::

The time taken by the clock signal to reach the sink flops from clock source is termed as the clock insertion delay, and the clock insertion delay is depending on two factors they are "Source latency delay" and "Network Latency delay". The relation goes this way:

clock insertion delay = Source latency delay + Network latency delay.

Source latency delay is the delay time of clock signal to reach from the clock generator source like (PLL) to Root pins (or) clock pins of the design.

Network latency delay is the delay time of clock signal to reach from the Root pins (or) clock pins of the design to the sink pins of flops in the design.

Clock Skew:

clock skew is defined as the difference of the insertion delays of two flops belonging to the same clock domain.
Skew is of two types 1) Local Skew
2) Global Skew

Local skew:
It is defined as the difference of insertion delays of two communicating flops of same clock domain.
Global skew:
It is defined as the difference between the delay times for earliest clock reaching flip-flop and latest clock reaching flip-flop for a same clock-domain.


Skew value can be +ve or -ve, as explained below.

if the capture flop receives clock signal late than the launch flop than it results in +ve skew.
if the launch flop receives clock signal late than the capture flop than it results in -ve skew.



Regards,
G.VENKATA KARTHIK,M.S.,VLSI
Hyderabad,
Last edited by karthik.venkata2020 on Mon Oct 12, 2015 12:40 pm, edited 2 times in total.

Arvind
Posts: 45
Joined: Wed Apr 09, 2014 3:11 pm
Location: Noida, India

Re: Differnce clock skew and clock insertion delay?

Post by Arvind » Fri Aug 08, 2014 11:07 am

Thanks Vimal & Karthik :)

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