why do we need virtual clock

Synthesis, timing closure, fixing setup & hold, constraints related questions can be asked here.
Post Reply
Netrapal
Posts: 19
Joined: Sat May 10, 2014 10:26 pm
Location: Gurgaon, India

why do we need virtual clock

Post by Netrapal »

what is meant by virtual clock definition and why do we need it?
arunvappukuttan
Posts: 2
Joined: Tue May 13, 2014 11:13 am

Re: why do we need virtual clock

Post by arunvappukuttan »

Virtual clock is a clock definition without a specific port or pin assigned to the definition . It is used for constraining input or output delays for a block . The advantage of defining a virtual clock is that we can specify our desired clock latency values for these virtual clock. Had this not been the case , the clock latency defined for the "real" clock to model the top level latency will be applied for the clock itself and hence all the registers to which the clock is reaching.
arushi
Posts: 5
Joined: Wed Apr 09, 2014 11:59 am

Re: why do we need virtual clock

Post by arushi »

There are three advantages of having the virtual clocks
1) Applying the clock latency as explained above
2) In case of the hierarchical designs , if a particular clock does not exist in a block , virtual clock of the same can be used to constrain the I/O ports.
3) It also helps in timing the half cycle and full cycle paths of the same clock.
Netrapal
Posts: 19
Joined: Sat May 10, 2014 10:26 pm
Location: Gurgaon, India

Re: why do we need virtual clock

Post by Netrapal »

Thanks Arun & Aru. :)
Post Reply