Page 1 of 1

Different Timing terminologies

Posted: Wed Jun 01, 2016 4:10 pm
Typical Clock Generation Scenario:The oscillator is external to the chip and produces a low frequency (10-50 MHz typical) clock which is used as a reference clock by the on-chip PLL to generate a high-frequency low-jitter clock (200-800 MHz typical). This PLL clock is then fed to a clock divider logic that generates the required clocks for the ASIC.

set_clock_transition:This specification applies only for ideal clocks and is disregarded once the clock trees are built.

set_clock_uncertainty:The uncertainty can be used to model various factors that can reduce the effective clock period.These factors can be the clock jitter and any other pessimism that one may want to include for timing analysis.Note that the clock uncertainty for setup effectively reduces the available clock period by the specified amount. For hold checks, the clock uncertainty for hold is used as an additional timing margin that needs to be satisfied.

set_clock_latency:There are two types of clock latencies: network latency and source latency. Network latency is the delay from the clock definition point (create_clock) to the clock pin of a flip-flop. Source latency, also called insertion delay, is the delay from the clock source to the clock definition point. Source latency could represent either on-chip or off-chip latency.The total clock latency at the clock pin of a flip-flop is the sum of the source and network latencies.The network latency is an estimate of the delay of the clock tree prior to clock tree synthesis.

create_generated_clock:A generated clock is a clock derived from a master clock. A master clock is a clock defined using the create_clock specification.For example, if there is a divide-by-3 circuitry for a clock, one would define a generated clock definition at the output of this circuitry.This definition is needed as STA does not know that the clock period has changed at the output of the divide-by logic, and more importantly what the new clock period is. Defining the new clock as a generated clock does not create a new clock domain, and the generated clock is considered
to be in phase with its master clock. In generated clocks source latency is already taken care with master clocks.