The response time of a hardware is always positive, then how the Setup and Hold times can be negative ?

What is the importance of this concept ?

## What is Negative Setup Time and Negative Hold Time Concept ?

### Re: What is Negative Setup Time and Negative Hold Time Conce

**Setup time**is the minimum amount of time data must be stable at input before arriving the active edge of the clock.

That is to say, if a flip-flop defines a 200 ps data setup time,then the data must arrive 200 ps before active edge of clock arrives.

**Hold time**is the minimum amount of time data must be stable at input after arriving the active edge of the clock.

i.e both setup and hold times are measured w.r.t the active egde of clock.

For a

**Pure flop**(containing no extra gates) setup and hold time always will be a positive number. Now, A flop can be a part of a bigger component.These components are available as a part of stranded cell library. Setup and hold time can be negative depending on where you measure the setup and hold time, if you measure setup and hold time at component level. These can be negative also.

Consider that a flop is sitting inside a component.

Given:

T_dataflop is the arrival time of data at the flop.

T_clkflop is the arrival time of clock edge at the flop.

T_flopsetup is the setup time of pure flop.

Therefore:

**Equation 1:**T_dataflop < = T_clkflop - T_flopsetup

That is to say.. "Data must arrive at the flop T_flopsetup(setup time) before the clock edge arrives". For example, say T_clkflop is 10 ns and T_flopsetup is 200 ps. In this case, T_dataflop must be less than 9.8 ns in order to meet setup timing.

With that in mind, let's factor component level timing:

T_datacomp is the arrival time of the data at the component pin.

T_clkcomp is the arrival time of the clock edge at the component pin.

T_datadelay is the delay of the data from the component pin to the embedded flop.

T_clkdelay is the delay of the clock from the component pin to the embedded flop.

By these definitions, we can say:

T_datacomp + T_datadelay = T_dataflop

T_clkcomp + T_clkdelay = T_clkflop

Therefore, substituting into Equation 1 from above,

**Equation 2:**T_datacomp + T_datadelay < = (T_clkcomp + T_clkdelay) - T_flopsetup

For illustration, assume that the following values were characterized (during product testing):

T_datadelay = 700 ps

T_clkdelay = 800 ps

T_flopsetup = 200 ps

Equation 2 becomes:

T_datacomp + 700 ps < = T_clkcomp + 800 ps - 200 ps

T_datacomp + 700 ps < = T_clkcomp + 600 ps

T_datacomp < = T_clkcomp - 100 ps

This implies a component level setup time of 100 ps.( Remember setup time pure flop is 200 ps)

Now assume that T_datadelay = 500 ps, and substitute into Eq 2:

T_datacomp + 500 ps < = T_clkcomp + 800 ns - 200 ps

T_datacomp + 500 ps < = T_clkcomp + 600 ps

T_datacomp <= T_clkcomp + 100 ps

This means that the data must arrive at the component 100 ps after the clock and thus we have a negative setup time.

Same way hold time also can be negative. Consider case: If add a buffer in front of flop which has delay greater than hold time of flop and measure the hold time at the input of buffer instead of FF then this become negative hold time with respect to the active edge of the clock. If this buffer is a part of FF then the hold time will negative.

There are many components available in stranded cell library that embed a flop inside. These components will be a part of our design. Static Timing Analysis(STA) tool check setup time violation at a component by finding the Slack

**Slack=Required arrival time of data-Actual arrival time of data.**This must be positive number. This means data must reach at required time or before to met setup.

For reg 2 reg path:

Required arrival time= Total period of clock - Setup time

Actual arrival time= Tclock>q+Tcomb. delay

So the value of setup and hold time is used by STA tool to calculate timing..

### Re: What is Negative Setup Time and Negative Hold Time Conce

Very nice explanation .. Thanks Narveer