What is a false path and what is multi-cycle path?

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Arvind
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What is a false path and what is multi-cycle path?

Post by Arvind » Wed Apr 09, 2014 3:42 pm

What is a false path and what is multi-cycle path?

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Narveer
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Re: What is a false path and what is multi-cycle path?

Post by Narveer » Wed Apr 09, 2014 4:12 pm

False path is that timing path for which STA tool is instructed to ignore its timing requirements (setup, hold). Typically false paths are present in the design because of the following reasons.

1) The path is functionally never exercised.
2) There are some unused ports of a reused IP which form these false paths.
3) Synthesis tool introduced flip-flops which break inadvertent combinational loops in the design which cause false paths.
4) Control signals that aid in the testability of the design should not be constrained during normal mode of operation, so mark them as false paths.

Multi-cycle path is one which takes more than one clock cycle to complete its operation. For example, an FSM produces enable signal for every 3 clock cycles and the o/p of a register is to samples only when this enable is high. So, this path having the register has to be declared as multi-cycle path in synthesis constraints. The input to this path should not change through out these 3 cycles.

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