IDDQ Testing Basics

SCAN, Boundary SCAN, MBIST, ATPG, JTAG, ATE, DFT simulations.
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RENU
Posts: 22
Joined: Mon Apr 07, 2014 11:18 pm

IDDQ Testing Basics

Post by RENU »

IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By this definition, all CMOS circuits are 100% IDDQ testable.

Faults detected by IDDQ tests:
Bridging Faults: Shorts between two nodes causing a voltage contention because they are being driven by two conflicting voltages. Sometimes also referred to as stuck-on faults.
Punch-through: Short between Drain and the source.
Resistive Shorts
Line and Gate Break Faults
Source or Drain Break Faults
Even some Delay Faults
Latch-Up
Stuck-open Faults
vikramrajput
Posts: 21
Joined: Mon Apr 06, 2015 9:30 pm

Re: IDDQ Testing Basics

Post by vikramrajput »

Hi Renu.

I heard that IDDQ testing was used long time ago, but now a days it is avoided due to decrease in the transistor size. And also heard that, it is a special type of testing performed to detect the faults which were not easily detected by the stuck at testing.

My question is , the faults which you have mentioned are they being detected now a days , as we are not performing this test ? Are they will be present in the design with out begin detected ? Or it is enough to perform only Stuck at and At speed testing to detect the faults in the design ?

Thanks in Advance.
RENU
Posts: 22
Joined: Mon Apr 07, 2014 11:18 pm

Re: IDDQ Testing Basics

Post by RENU »

Hi Vikram,

You are right IDDQ fault testing is for faults which are not detected by stuckat fault type. It is like top-up patterns. Also, Bridging faults and punch trough faults can be detected by these patterns.So, we use IDDQ patterns for additional fault coverage.

Regards,
Renu
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