Test Pattern Simulation

SCAN, Boundary SCAN, MBIST, ATPG, JTAG, ATE, DFT simulations.
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vikramrajput
Posts: 21
Joined: Mon Apr 06, 2015 9:30 pm

Test Pattern Simulation

Post by vikramrajput » Mon Feb 22, 2016 7:49 pm

Hello there,

can any one tell me about the mismatches occurred during zero delay simulation after pattern generation in ATPG. As I know there is one mismatch due to pin constraints / cut points. Is there any other mismatch ?

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