1. how do we perform parallel simulation and serial simulation in VCS. what is the process and inputs should we take care of ?
2. how do we debug any timing simulation fails at silicon with timing and no timing simulation process ?
3. what is chain pattern test ?
4. even after STA timing closer why we perform timing checks at dft level ?
SCAN, Boundary SCAN, MBIST, ATPG, JTAG, ATE, DFT simulations.
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