low power design techniques in vlsi
low power design techniques in vlsi
What are various low power design techniques used in vlsi design?
Re: low power design techniques in vlsi
Below are various low power techniques.
Design Level: Multi VT, clock gating, power gating, multi VDD and Dynamic Voltage and Frequency Scaling (DVFS).
Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET.
Search in google to know details of each technique.
http://vlsi-soc.blogspot.in/2012/08/clo ... -cell.html
http://vlsi-soc.blogspot.in/2012/07/clock-gating.html
http://vlsi-soc.blogspot.in/2012/08/power-gating.html
http://vlsi-soc.blogspot.in/2013/03/sta ... ating.html
Design Level: Multi VT, clock gating, power gating, multi VDD and Dynamic Voltage and Frequency Scaling (DVFS).
Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET.
Search in google to know details of each technique.
http://vlsi-soc.blogspot.in/2012/08/clo ... -cell.html
http://vlsi-soc.blogspot.in/2012/07/clock-gating.html
http://vlsi-soc.blogspot.in/2012/08/power-gating.html
http://vlsi-soc.blogspot.in/2013/03/sta ... ating.html