Design How-To 2D vs. 2.5D vs. 3D ICs 101

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Design How-To 2D vs. 2.5D vs. 3D ICs 101

Post by bprasad2005 » Mon Jul 07, 2014 7:36 am

2D vs. 2.5D vs. 3D ICs 101
Clive Maxfield
I see a lot of articles bouncing around the Internet these days about 2.5D and 3D ICs. One really good one that came out recently was 2.5D ICs are more than a stepping stone to 3D ICs by Mike Santarini of Xilinx. On the other hand, there are a lot of other articles that have “3D ICs” in the title, but when I plunge in I realize that we’re really only talking about 2.5D ICs.

The problem is that there’s a lot of confusion in this area. While chatting to people I find that they typically either know this stuff “inside and out” … or they are somewhat baffled and bewildered. Thus, I decided to pen a few words on the subject to explain the way in which I see things. The following is “off the top of my head”, so please feel free to comment saying whether you agree or disagree with my meandering musings.

But before we plunge headfirst into the fray with gusto and abandon, let’s pause for a moment to ponder the “101” portion of this column’s title. The use of “101”, which you see all over the place, is intuitively obvious to an American audience, but it can cause confusion to folks from other countries, who end up fixating on the hidden meaning behind the “101” to the exclusion of the rest of the article.

This really is very simple. It used to be common for colleges in America to give their various courses numbers: the 100-series for the first year, the 200-series for the second, the 300-series for the third, and so forth. The -01 course would be the simplest course or the foundation module that everybody had to take, so "Something 101" refers to a basic introduction. There… you see… that wasn’t too bad, was it?

Each function in its own chip package
OK, let’s take things from the top. Not-so-long-ago, different functions like high-performance logic, lower-performance logic, memory, and analog/RF were each presented as discrete devices in their own chip packages as illustrated below:

Birds-eye view of circuit board
with individually packaged chips

There were several advantages to this scenario, such as the fact that different chip companies could concentrate on creating devices that fell into their realm of expertise. Also, each chip die could be implemented at the most appropriate technology node. The high-performance digital logic chip could be created at the latest-and-greatest (and more expensive) technology node, for example, while the lower-performance digital logic device could be created using an earlier (and more affordable) technology node.

Of course there are also disadvantages to this approach, such as the fact that the resulting circuit board will be larger, heavier, and consume more power. Also every soldered joint on the board is a potential point of failure. Furthermore, there’s a significant hit in performance, because it takes a relatively long time in the scheme of things for signals to propagate across the board from one chip package to another.

Multi-chip modules (MCMs) and hybrids
Sometime around the beginning of the 1990s we saw the advent of devices known as multi-chip modules (MCMs). To the best of my recollection, these typically involved a number of digital-only dice* mounted on the same package substrate. And speaking of package substrates (meaning the base layer), a variety of materials could be used, ranging from silicon to super-thin laminates (like little printed circuit boards), all presented in ceramic, metallic, or even plastic packages. [*Dies is used as the plural for die in the sense of a mold, while dice is used as the plural (and increasingly as the singular) in the sense of a small random number generator (on gambling and games, we may roll one die or toss two or more dice). Dice is also the accepted plural form of die in the semiconductor industry.]

In addition to MCMs we also had hybrids (actually hybrids predate MCMs by several decades). As I wrote in my book Bebop to the Boolean Boogie (An Unconventional Guide to Electronics):

The word hybrid is defined as “the offspring resulting from crossbreeding.” Many would agree that this is an apt description for the species of electronic entities known as hybrids, which combine esoteric mixtures of interconnection and packaging technologies. In electronic terms, a hybrid consists of a collection of components mounted on a single insulating base layer called the substrate. A typical hybrid may contain a number of packaged or un-packaged integrated circuits and a variety of discrete components such as resistors, capacitors, and inductors, all attached directly to the substrate. Connections between the components are formed on the surface of the substrate; also, some components such as resistors and inductors may be fabricated directly onto the surface of the substrate.

Actually, if you want to know more about things like hybrids, may I be so bold as to casually mention that they are discussed in excruciating detail in Bebop to the Boolean Boogie (the only electronics book to boast an amazing Seafood Gumbo recipe).

System-on-Chip (SoC) devices
The next step was to create System-on-Chip (SoC) devices, in which all of the functions are implemented on a single die as illustrated below:

Birds-eye view of circuit board with
a System-on-Chip (SoC) device

Different people have different definitions as to exactly what comprises an SoC. A digital logic designer might say that an SoC contains one or more processor cores, memory blocks, peripheral functions, and hardware accelerators, all created on the same piece of silicon. By comparison, someone like a system architect looking at things from a slightly higher vantage point might say that an SoC is a single device that combines digital logic, memory, and analog/RF functions all on the same die.

The advantage of an SoC is that you get the highest performance with the lowest power consumption – at least you do for the digital portions of the device. The disadvantage is that creating one of these little rascals is horrendously complicated, resource intensive, and time consuming. Also, adding analog and RF functions on the same die as the digital logic my mean that (a) the analog/RF functions aren’t as optimal as they could be if implemented using a dedicated process and (b) you can run into all sorts of noise and isolation problems. And yet another consideration is the time and expense involved in re-spinning the design in the future to evolve existing functionality or add new features.

Now, before we proceed, I should point out that things aren’t quite as “black-and-white” as I’m presenting them here with regard to the timeline. In reality, it’s all much more of a “gray smear” with different companies introducing different packaging styles at different times. For example, you might think the concept of placing bare die directly onto a circuit board – Chip-on-Board (COB) – is relatively modern, but we [the company I was working for at the time] were doing this as far back as 1980. The bottom line is that when I say something like “This technique started in the early 1990s and faded out at the end of the 1990s,” it’s more than possible that some companies were doing it before that time and other companies are still doing it to this day.

System-in-Package (SiP) assemblies
There’s an old expression “What goes around comes around,” which loosely means that the status of something eventually returns to its original value after completing some sort of a cycle. This is the way I sort of think about the concept of a System-in-Package (SiP), whose name started to gain traction around the year 2000, and which may be considered to be the modern incarnation of a multi-chip module (MCM).

The idea behind a SiP is that multiple bare dice and/or chip-scale package (CSP) devices are mounted on a common substrate, which is used to connect them all together. The substrate and its components are then placed in (or built into) a single package as illustrated below:

Birds-eye view of circuit board with
a System-in-Package (SiP) device

This approach has several advantages over a System-on-Chip (SoC), including the fact that one can include analog, digital, and radio frequency (RF) dice in the same package, where each die is implemented using that domain's most appropriate technology process. Also, designers can employ a number of off-the-shelf dice coupled, perhaps, with a limited number of relatively small, internally-developed components. Furthermore, when it comes to re-spinning the device in the future to evolve existing functionality or add new features, it may well be the case that you need modify only a subset of the dice.

While we’re talking about SiPs, we might as well make note of the fact that a wide variety of substrates may be used for SiP assemblies depending on the requirements of the particular application. For example, some of the more common possibilities are as follows:

Laminates such as small, fine-line printed circuit boards with copper tracks and copper vias. These are usually made out of FR4 or polyimide and typically contain 5 to 25 tracking layers.
Ceramic substrates, some of which are similar to those used for hybrids: that is, formed from a single, seamless piece of ceramic and carrying tracks that are created using thick-film** or thin-film** processes (or a mixture of both). However, a large proportion of ceramic multichip modules are of the cofired** variety, in which case they are formed from a material such as aluminum nitride or beryllium oxide and can contain hundreds of layers. (**I’m sure it won’t surprise you to learn that topics like thick-film, thin-film, and co-fired ceramics are more fully explained in Bebop to the Boolean Boogie [grin])
Ceramic, glass, or metal substrates that are covered with a layer of dielectric material such as polyimide. The dielectric coat is used to modify the substrate’s capacitive characteristics and tracks are created on the surface of the dielectric using thin-film processes. Substrates of this type typically have around five tracking layers.
Semiconductor substrates, predominantly silicon, with very fine tracks formed using opto-lithographic processes similar to those used for integrated circuits. Semiconductor substrates are also known as active substrates, because components such as transistors and logic gates can be fabricated directly onto their surface. One additional benefit of using silicon as a substrate is that its coefficient of thermal expansion exactly matches that of any silicon chips that are attached to it.

And before we move on, just to increase the fun and frivolity, it’s possible to create a number of small SiPs and then mount these in a larger SiP, in which case we have a scenario known as Package-in-Package (PiP). Also, in some cases, we have a SiP that is mounted on top of another SiP, which some refer to as a Package-on-Package (PoP).

2.5D Integrated Circuits
All of the previous packaging technologies fall under the realm of 2D (two-dimensional) ICs, because the die or dice are mounted in the package in a single plane. Let’s take this part of our discussions step-by-step, because it’s easy to get confused. Let’s start with a traditional 2D IC/SiP as illustrated below:

A traditional 2D IC/SiP

For the sake of simplicity we are showing only two dice in the SiP, but there could be many more. Also, in this example we are assuming that the dice are mounted on the SiP substrate using flip-chip technology (wire-bond technology could also be used); in this case the flip-chip solder bumps will be ~100um in diameter. Let’s also assume that the SiP substrate is of the laminate variety; that is, as small, fine-line printed circuit board with copper tracks and copper vias containing a number of tracking layers. Although this form of SiP technology really is incredibly impressive, the tracks on the SiP substrate are orders of magnitude larger than the tracks on the silicon dice. This discrepancy in size impacts performance and power consumption. Also, the larger tracks on the SiP substrate lead to routing congestion that places limitations on the number of die-to-die connections that can be realized.

All of which leads us to the concept of a 2.5D IC/SiP. The main difference between a traditional 2D IC/SiP as shown above and a 2.5D IC/SiP as shown below is that, in the case of the 2.5D version, a silicon interposer is placed between the SiP substrate and the dice, where this silicon interposer has through-silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces.

A 2.5D IC/SiP using a silicon interposer
and through-silicon vias (TSVs)

In this case, the dice are attached to the silicon interposer using micro-bumps, which are ~10um in diameter. Meanwhile, the silicon interposer is attached to the SiP substrate using regular flip-chip bumps, which will be ~100um in diameter. The tracks on the silicon interposer’s topside and backside metal layers (there can be multiple metal layers in both cases) are created using the same processes as the tracks on the silicon chips.

Although the silicon interposer and the silicon dice in the image above appear to be a little “chunky”, you have to remember that this drawing is not to scale. In reality, the dice are only ~0.2mm thick, while the silicon interposer is not much thicker.

As one example of the use of this technology, the Xilinx Virtex-7 2000T device has four FPGA dice attached to a silicon interposer, which supports ~10,000 silicon-speed connections between adjacent dice.

The advantage of using 2.5D IC/SiP technology is that it’s an incremental step from traditional 2D IC/SiP technology that offers tremendous increases in capacity and performance. There are also yield advantages, because it’s easier to make a number of small dice as opposed to a single large one. The main disadvantage is that it’s non-trivial to make all of this work (“If it was easy, everyone would be doing it,” as the old saying goes).

3D Integrated Circuits
And so, finally, we arrive at 3D integrated circuits. The idea behind 3D ICs/SiPs is to mount two or more dice on top of each other. An individual die is now so thin that theoretically it would be possible to mount 100 on top of each other to form a cube, but the amount of heat being generated would melt the resulting structure into a puddle of silicon in a very short time. One solution might be to create the dice using diamond as the substrate, but that’s story for another day.

Actually, 3D ICs aren’t new; there have been several variations on this theme over the years. It is not uncommon, for example, to mount one die on the SiP substrate using flip-chip technology, and to then mount a second die on top of the first using wire-bond technology as shown below:

A simple form of 3D IC/SiP

Another technique is to take a group of dice that all perform an identical function (like memory chips, for example), to build them into a 3D stack, and to run the wires down the sides as illustrated below:

Connecting dice using wires running down the sides

But none of these techniques are what we are talking about here. In a modern context, what we might call a “True 3D IC” will involve at least one die being mounted on the top of another die, with the lower die employing through-silicon vias (TSVs) to allow the upper die to communicate with the lower die and the SiP substrate as illustrated below:

A simple “True 3D IC/SiP”

So, for example, we could have a memory die attached to a logic die (or vice versa), or an analog/RF die attached to a digital logic die, or… just imagine your own scenario.

The previous image showed the simplest example of this technology. My own personal interpretation of a “True 3D IC” would be one in which multiple dice are stacked on top of each other using TSVs, and multiple groups of dice are connected together using a silicon interposer, all mounted in a single SiP as illustrated below:

A more complex “True 3D IC/SiP”

Once again, although this drawing may seem a little “clunky”, you have to remember that the dice are only ~0.2mm thick and the silicon interposer is not much thicker, so the entire assembly shown above would be much smaller than you might suppose.

OK. That’s my humble interpretation of, and introduction to, 2D vs. 2.5D vs. 3D ICs. Do you agree, or do you see things differently?

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Posts: 35
Joined: Tue Apr 08, 2014 5:13 pm
Location: kurukshetra

2.5D ICs are more than a stepping stone to 3D ICs

Post by bprasad2005 » Mon Jul 07, 2014 7:38 am

2.5D ICs are more than a stepping stone to 3D ICs
Mike Santarini, Xilinx

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