Stitching of positive & negative flops in a scan chain?
Stitching of positive & negative flops in a scan chain?
Why we don't stitch positive edge flops then negative edge flops in a scan chain ?
-
- Posts: 21
- Joined: Mon Apr 06, 2015 9:30 pm
Re: Stitching of positive & negative flops in a scan chain?
Hi ,
Actually we can have three combinations:
1) All positive
2) All negative
3) Negative followed by positive
but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not possible. We will require lock up latch.
The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge then you a lock up latch (if skew is small)
this depends on the nature of clock involved in your scan design.
Clock nature
1 : RTZ then chain should be : negedge ->posedge
2 : non RTZ thene it shoul be vice-versa
reason is value loaded on first flop shhuld not passed on to next FF in same cycle.
Actually we can have three combinations:
1) All positive
2) All negative
3) Negative followed by positive
but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not be captured. Since at single pulse data launch and capture is not possible. We will require lock up latch.
The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge then you a lock up latch (if skew is small)
this depends on the nature of clock involved in your scan design.
Clock nature
1 : RTZ then chain should be : negedge ->posedge
2 : non RTZ thene it shoul be vice-versa
reason is value loaded on first flop shhuld not passed on to next FF in same cycle.